A schematic block diagram of a configuration including a video camera and a host computer is illustrated in FIG. 1. The video camera 10 includes a charge-coupled device (CCD) 12 and is coupled to the host computer 20 for providing video data from the video camera 10 to the host computer 20. Within the video camera 10, the CCD 12 is coupled to a timing chip 14 which provides a clocking signal to the CCD 12. The CCD 12 is also coupled to a sample and hold and analog-to-digital converter circuit 16. The CCD 12 provides image data at a rate determined by the timing chip 14 to the sample and hold and analog-to-digital converter circuit 16. This image data is then sampled and converted into a digital format by the sample and hold and analog-to-digital converter circuit 16. The sample and hold and analog-to-digital converter circuit 16 is coupled to a digital signal processing (DSP) circuit 18. The DSP circuit 18 receives the digital data from the sample and hold and analog-to-digital converter circuit 16 and converts it into an appropriate video format, such as RGB, YC.sub.R C.sub.B, NTSC, PAL or any other appropriate format. The DSP circuit 18 is then coupled to an interface circuit 19 for providing the video data for transmission from the video camera 10 to a device coupled to the video camera 10.
In the configuration illustrated in FIG. 1, the video camera 10 is a stand-alone camera and is coupled to a host computer 20 through which the video data transmitted from the video camera 10 can be displayed on an associated display 36, saved and/or transmitted to another device. The interface circuit 19 of the video camera 10 is coupled to an interface circuit 28 of the host computer 20 by a bus or cable for transmitting the video data from the video camera 10 to the host computer 20. The host computer system 20, illustrated in FIG. 1, is exemplary only and includes a central processor unit (CPU) 42, a main memory 30, a video graphics adapter (VGA) card 22, a mass storage device 32 and an interface circuit 28, all coupled together by a conventional bidirectional system bus 34. The mass storage device 32 may include both fixed and removable media using any one or more of magnetic, optical or magneto-optical storage technology or any other available mass storage technology. The system bus 34 contains an address bus for addressing any portion of the memory 30. The system bus 34 also includes a data bus for transferring data between and among the CPU 42, the main memory 30, the VGA card 22, the mass storage device 32 and the interface circuit 28.
The host computer system 20 is also coupled to a number of peripheral input and output devices including the keyboard 38, the mouse 40 and the associated display 36. The keyboard 38 is coupled to the CPU 42 for allowing a user to input data and control commands into the computer system 20. A conventional mouse 40 is coupled to the keyboard 38 for manipulating graphic images on the display 36 as a cursor control device.
The VGA card 22 interfaces between the components within the computer system 20 and the display 36. The VGA card 22 converts data received from the components within the computer system 20 into signals which are used by the display 36 to generate images for display.
In the configuration illustrated in FIG. 1, the data read out from the CCD 12 is provided to the sample and hold and analog-to-digital converter circuit 16 where it is converted into a digital format. This digital data is raw video data representing the data read out from the CCD 12. This digital data from the sample and hold and analog-to-digital converter circuit 16 is provided to the DSP circuit 18 where it is converted into the appropriate video data format before it is transmitted from the video camera 10. As described above, the appropriate video format can include RGB, YC.sub.R C.sub.B, NTSC, PAL or any other appropriate format. Assuming eight (8) bit resolution per each color component or raw data, data in the RGB format requires twenty-four (24) bits per pixel and therefore three times as much bandwidth for transmission as the raw video data. Correspondingly, data in the YC.sub.R C.sub.B (4:2:2) format requires sixteen (16) bits per pixel and therefore one and a half to two times as much bandwidth for transmission compared to the raw video data. In systems with ever increasing image size, pixel density and limited transmission bandwidth capabilities, it is desirable to transmit the raw video data from a video camera because it is the format requiring the lowest data rate and correspondingly, the least bandwidth. Typical systems which receive video data from devices such as a video camera, however, are not equipped to process the raw video data and convert it into the appropriate format for display. Accordingly, transmission of the raw video data from a CCD camera to a receiving device is not used in typical systems.
Typical consumer video cameras, such as the camera 10, maintain automatic control over the main functions and settings of the camera, including control of the iris or electronic shutter speed, control of the automatic gain control (AGC) to obtain the proper signal level, back light compensation, and auto white balance. Typically, the camera will determine the proper back light compensation based on some selected frames of video data. The auto white balance is performed automatically by the camera, assuming it can determine which areas within the picture should be white. All of these control functions are performed automatically by the DSP circuit 18 with no involvement from the user.
The CCD 12 typically includes a Yellow-Cyan-Magenta-Green mosaic color filter, as is well known in the art. Using this mosaic filter, the CCD 12 captures color images and outputs data representing the color images. The color image data from the CCD 12 is combined into a tile structure, as illustrated in FIG. 2. This tile structure 50 provides raw video data representing the image captured by the CCD 12. From this tile structure 50, the luminance and chrominance components for the video data are obtained. Within the tile structure 50, pixels representing different colors are arranged adjacent to each other.
The raw video data in the tile structure of the CCD color space cannot be scaled or compressed without violating the tile structure of the frame represented by the raw video data. Compression requires a correlation of data between adjacent pixels, either horizontally or vertically. Data in the tile structure of the CCD color space does include some correlation. However, in its regular format, direct manipulation of raw data pixels in the tile structure of the CCD color space will lead to severe color and luminance errors, due to the adjacent relationship of colored pixels of different colors within the tile structure.
As with many other devices, the size and weight of the video camera are important characteristics considered by a system designer or perspective purchaser. It is therefore desirable to minimize the size and weight of the video camera where it is feasible and appropriate. Including the DSP circuit 18 within the camera 10 and requiring the processing of the video data to be completed within the camera 10 increases the necessary size of the video camera 10 and thereby also increases its weight.
What is needed is a video camera which can be easily integrated into a supporting device, such as a personal computer. What is further needed is a video camera which will transmit raw video data to the supporting device where it can then be appropriately converted and processed into the proper video format. What is still further needed is a graphical user interface which allows a user to easily control and monitor the operation of a video camera.